1. Field of the Invention
One embodiment of the present invention relates to a memory device including a semiconductor or a semiconductor device, a driving method thereof, a manufacturing method thereof, and the like.
Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in the specification, the drawings, and the claims (hereinafter referred to as “this specification and the like”) relates to an object, a method, or a manufacturing method. Furthermore, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a memory device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, an input device, an imaging device, a method of driving any of them, and a method of manufacturing any of them.
2. Description of the Related Art
In a general dynamic random access memory (DRAM), a memory cell includes one writing transistor (1T) and one capacitor (1C). Such a 1T1C DRAM is a memory capable of retaining data by accumulating charge in the capacitor and thus has no limit on the number of times of writing in principle. As a high-capacity memory device, the DRAM is incorporated in a number of electronic appliances because of writing and reading at relatively high speed and a small number of memory cells, which easily enable high integration. Besides the 1T1C memory cell, a memory cell called a gain cell including two or three transistors is known.
Even when a writing transistor is in an off state, a slight amount of leakage current is generated between a source and a drain; thus, the data is lost within a relatively short time. Therefore, the data needs to be rewritten (refreshed) on a regular cycle (generally once every several tens of milliseconds) in a DRAM.
The use of a transistor in which the channel is formed using an oxide semiconductor (hereinafter may be referred to as an OS transistor) in a 1T1C memory cell and the use of the OS transistor as a writing transistor of a gain cell are proposed. For example, Patent Document 1 discloses that even when power is not supplied, data can be retained in a memory cell for a long period by utilization of a characteristic of an extremely small off-state current of an OS transistor. Furthermore, a circuit which has a function of detecting the timing of refresh of a memory cell including an OS transistor is proposed (e.g., Patent Documents 2 and 3).